Design Verification Engineer - #2181730

Principal Verification Engineer

Location: Edinburgh, Scotland

An exciting opportunity has arisen for an experienced Principal Verification Engineer to join a leading global semiconductor technology company in Edinburgh, working on advanced Chiplet and IP development.

This position sits within an established, international engineering team developing complex, next-generation semiconductor technology.

The role offers the opportunity to work across a broad range of verification methodologies, combining simulation, Formal Verification and hardware emulation. You'll have significant technical ownership, working closely with architects and design engineers to develop robust verification environments and tackle complex design challenges.

Key Responsibilities

• Develop verification and emulation environments for complex Chiplet designs.
• Design and implement SystemVerilog/UVM scoreboards and self-checking regression environments.
• Develop functional coverage models and contribute to Metric Driven Verification (MDV) methodologies.
• Create SystemVerilog Assertions (SVA) for Formal Verification and simulation.
• Develop and integrate hardware emulation environments.
• Integrate Verification IP (VIP) and accelerated VIP into simulation and emulation environments.
• Define and manage verification plans, ensuring comprehensive coverage and verification closure.
• Collaborate closely with architects and RTL design engineers to investigate and resolve complex verification challenges.
• Participate in technical design reviews and contribute to verification best practices.

Required Experience

• Degree in Electrical/Electronic Engineering, Microelectronics or a related discipline.
• 8+ years of experience within semiconductor design, verification or the EDA industry.
• Strong experience in functional verification using SystemVerilog and UVM.
• Proven experience with Metric Driven Verification (MDV), including functional coverage and verification planning.
• Practical experience with Formal Verification methodologies and SystemVerilog Assertions.
• Experience developing verification environments for complex ASIC, SoC or IP designs.

This is an opportunity to move beyond traditional simulation-based verification and work across multiple verification methodologies on advanced semiconductor technology.

You'll join a highly experienced international engineering organisation, with the opportunity to influence verification strategy, take ownership of technically challenging projects and contribute to the development of next-generation Chiplet solutions.

For an experienced Verification Engineer looking to remain technically hands-on while taking on greater responsibility and influence, this could be an excellent next step.

Interested in finding out more?

Please contact Rachel Mason at IC Resources for a confidential discussion.

[email protected]